dorsal/arxiv
View SchemaLAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsigns
| Authors | Deeksha Nandal, Riccardo Revalor, Soham Dan, Debjit Pal |
|---|---|
| Categories | |
| ArXiv ID | 2601.08856vv1 |
| URL | https://arxiv.org/abs/2601.08856 |
| License | http://creativecommons.org/licenses/by-nc-sa/4.0/ |
Abstract
Unit tests are critical in the hardware design lifecycle to ensure that component design modules are functionally correct and conform to the specification before they are integrated at the system level. Thus developing unit tests targeting various design features requires deep understanding of the design functionality and creativity. When one or more unit tests expose a design failure, the debugging engineer needs to diagnose, localize, and debug the failure to ensure design correctness, which is often a painstaking and intense process. In this work, we introduce LAUDE, a unified unit-test generation and debugging framework for hardware designs that cross-pollinates the semantic understanding of the design source code with the Chain-of-Thought (CoT) reasoning capabilities of foundational Large-Language Models (LLMs). LAUDE integrates prompt engineering and design execution information to enhance its unit test generation accuracy and code debuggability. We apply LAUDE with closed- and open-source LLMs to a large corpus of buggy hardware design codes derived from the VerilogEval dataset, where generated unit tests detected bugs in up to 100% and 93% of combinational and sequential designs and debugged up to 93% and 84% of combinational and sequential designs, respectively.
{
"annotation_id": "060fcd7b-d420-48a2-96ef-e51c2ef0608c",
"date_created": "2026-02-17T05:53:20.169000Z",
"date_modified": "2026-02-17T05:53:20.169000Z",
"file_hash": "25ce01b747d41323cd125a36c14623d47786a4f8406165950bd730645919ebc3",
"private": false,
"record": {
"abstract": "Unit tests are critical in the hardware design lifecycle to ensure that component design modules are functionally correct and conform to the specification before they are integrated at the system level. Thus developing unit tests targeting various design features requires deep understanding of the design functionality and creativity. When one or more unit tests expose a design failure, the debugging engineer needs to diagnose, localize, and debug the failure to ensure design correctness, which is often a painstaking and intense process. In this work, we introduce LAUDE, a unified unit-test generation and debugging framework for hardware designs that cross-pollinates the semantic understanding of the design source code with the Chain-of-Thought (CoT) reasoning capabilities of foundational Large-Language Models (LLMs). LAUDE integrates prompt engineering and design execution information to enhance its unit test generation accuracy and code debuggability. We apply LAUDE with closed- and open-source LLMs to a large corpus of buggy hardware design codes derived from the VerilogEval dataset, where generated unit tests detected bugs in up to 100% and 93% of combinational and sequential designs and debugged up to 93% and 84% of combinational and sequential designs, respectively.",
"arxiv_id": "2601.08856",
"authors": [
"Deeksha Nandal",
"Riccardo Revalor",
"Soham Dan",
"Debjit Pal"
],
"categories": [
"cs.SE",
"cs.AI"
],
"license": "http://creativecommons.org/licenses/by-nc-sa/4.0/",
"title": "LAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsigns",
"url": "https://arxiv.org/abs/2601.08856",
"version": "v1"
},
"schema_id": "dorsal/arxiv",
"source": {
"execution_id": "0c706121-a50d-44bc-8b67-88a1dd8d9e3c",
"id": "arXiv Dataset",
"type": "Model",
"variant": "snapshot-2026-01-17",
"version": "0.1.0"
},
"user_id": 1000002
}